circuit mycompareFIFOs :
  extmodule ResetCounter :
    input clk : Clock
    input reset : UInt<1>
    output timeSinceReset : UInt<32>
    output notChaos : UInt<1>
    defname = ResetCounter

  module srFIFO :
    input clock : Clock
    input reset : Reset
    output io : { flip dataIn : UInt<4>, flip push : UInt<1>, flip pop : UInt<1>, dataOut : UInt<4>, full : UInt<1>, empty : UInt<1>}

    cmem memRegs : UInt<4> [8] @[FIFOs.scala 50:20]
    reg tailReg : UInt<3>, clock with :
      reset => (reset, UInt<3>("h0")) @[FIFOs.scala 52:24]
    reg emptyReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[FIFOs.scala 53:25]
    node _T = eq(io.full, UInt<1>("h0")) @[FIFOs.scala 55:18]
    node _T_1 = and(io.push, _T) @[FIFOs.scala 55:16]
    when _T_1 : @[FIFOs.scala 55:28]
      infer mport MPORT = memRegs[UInt<3>("h7")], clock @[FIFOs.scala 57:14]
      infer mport MPORT_1 = memRegs[UInt<3>("h6")], clock @[FIFOs.scala 57:28]
      MPORT <= MPORT_1 @[FIFOs.scala 57:18]
      infer mport MPORT_2 = memRegs[UInt<3>("h6")], clock @[FIFOs.scala 57:14]
      infer mport MPORT_3 = memRegs[UInt<3>("h5")], clock @[FIFOs.scala 57:28]
      MPORT_2 <= MPORT_3 @[FIFOs.scala 57:18]
      infer mport MPORT_4 = memRegs[UInt<3>("h5")], clock @[FIFOs.scala 57:14]
      infer mport MPORT_5 = memRegs[UInt<3>("h4")], clock @[FIFOs.scala 57:28]
      MPORT_4 <= MPORT_5 @[FIFOs.scala 57:18]
      infer mport MPORT_6 = memRegs[UInt<3>("h4")], clock @[FIFOs.scala 57:14]
      infer mport MPORT_7 = memRegs[UInt<2>("h3")], clock @[FIFOs.scala 57:28]
      MPORT_6 <= MPORT_7 @[FIFOs.scala 57:18]
      infer mport MPORT_8 = memRegs[UInt<2>("h3")], clock @[FIFOs.scala 57:14]
      infer mport MPORT_9 = memRegs[UInt<2>("h2")], clock @[FIFOs.scala 57:28]
      MPORT_8 <= MPORT_9 @[FIFOs.scala 57:18]
      infer mport MPORT_10 = memRegs[UInt<2>("h2")], clock @[FIFOs.scala 57:14]
      infer mport MPORT_11 = memRegs[UInt<1>("h1")], clock @[FIFOs.scala 57:28]
      MPORT_10 <= MPORT_11 @[FIFOs.scala 57:18]
      infer mport MPORT_12 = memRegs[UInt<1>("h1")], clock @[FIFOs.scala 57:14]
      infer mport MPORT_13 = memRegs[UInt<1>("h0")], clock @[FIFOs.scala 57:28]
      MPORT_12 <= MPORT_13 @[FIFOs.scala 57:18]
      infer mport MPORT_14 = memRegs[UInt<1>("h0")], clock @[FIFOs.scala 59:12]
      MPORT_14 <= io.dataIn @[FIFOs.scala 59:16]
      node _T_2 = eq(emptyReg, UInt<1>("h0")) @[FIFOs.scala 60:10]
      when _T_2 : @[FIFOs.scala 60:21]
        node _tailReg_T = add(tailReg, UInt<1>("h1")) @[FIFOs.scala 61:26]
        node _tailReg_T_1 = tail(_tailReg_T, 1) @[FIFOs.scala 61:26]
        tailReg <= _tailReg_T_1 @[FIFOs.scala 61:15]
      emptyReg <= UInt<1>("h0") @[FIFOs.scala 63:14]
    else :
      node _T_3 = eq(emptyReg, UInt<1>("h0")) @[FIFOs.scala 64:23]
      node _T_4 = and(io.pop, _T_3) @[FIFOs.scala 64:21]
      when _T_4 : @[FIFOs.scala 64:34]
        node _T_5 = eq(tailReg, UInt<1>("h0")) @[FIFOs.scala 65:18]
        when _T_5 : @[FIFOs.scala 65:27]
          emptyReg <= UInt<1>("h1") @[FIFOs.scala 66:16]
        node _T_6 = eq(tailReg, UInt<1>("h0")) @[FIFOs.scala 68:18]
        when _T_6 : @[FIFOs.scala 68:27]
          emptyReg <= UInt<1>("h1") @[FIFOs.scala 69:16]
        else :
          node _tailReg_T_2 = sub(tailReg, UInt<1>("h1")) @[FIFOs.scala 71:26]
          node _tailReg_T_3 = tail(_tailReg_T_2, 1) @[FIFOs.scala 71:26]
          tailReg <= _tailReg_T_3 @[FIFOs.scala 71:15]
    infer mport io_dataOut_MPORT = memRegs[tailReg], clock @[FIFOs.scala 75:24]
    io.dataOut <= io_dataOut_MPORT @[FIFOs.scala 75:14]
    io.empty <= emptyReg @[FIFOs.scala 76:12]
    node _io_full_T = eq(tailReg, UInt<3>("h7")) @[FIFOs.scala 77:22]
    io.full <= _io_full_T @[FIFOs.scala 77:11]

  module rbFIFO :
    input clock : Clock
    input reset : Reset
    output io : { flip dataIn : UInt<4>, flip push : UInt<1>, flip pop : UInt<1>, dataOut : UInt<4>, full : UInt<1>, empty : UInt<1>}

    cmem memRegs : UInt<4> [8] @[FIFOs.scala 97:20]
    reg tailReg : UInt<3>, clock with :
      reset => (reset, UInt<3>("h0")) @[FIFOs.scala 98:24]
    reg headReg : UInt<3>, clock with :
      reset => (reset, UInt<3>("h0")) @[FIFOs.scala 99:24]
    reg emptyReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h1")) @[FIFOs.scala 100:25]
    node _T = eq(io.full, UInt<1>("h0")) @[FIFOs.scala 102:18]
    node _T_1 = and(io.push, _T) @[FIFOs.scala 102:16]
    when _T_1 : @[FIFOs.scala 102:28]
      infer mport MPORT = memRegs[headReg], clock @[FIFOs.scala 103:12]
      MPORT <= io.dataIn @[FIFOs.scala 103:22]
      node _headReg_T = add(headReg, UInt<1>("h1")) @[FIFOs.scala 104:24]
      node _headReg_T_1 = tail(_headReg_T, 1) @[FIFOs.scala 104:24]
      headReg <= _headReg_T_1 @[FIFOs.scala 104:13]
      emptyReg <= UInt<1>("h0") @[FIFOs.scala 105:14]
    else :
      node _T_2 = eq(emptyReg, UInt<1>("h0")) @[FIFOs.scala 106:23]
      node _T_3 = and(io.pop, _T_2) @[FIFOs.scala 106:21]
      when _T_3 : @[FIFOs.scala 106:34]
        node _tailReg_T = add(tailReg, UInt<1>("h1")) @[FIFOs.scala 107:24]
        node _tailReg_T_1 = tail(_tailReg_T, 1) @[FIFOs.scala 107:24]
        tailReg <= _tailReg_T_1 @[FIFOs.scala 107:13]
        node _T_4 = add(tailReg, UInt<1>("h1")) @[FIFOs.scala 108:19]
        node _T_5 = tail(_T_4, 1) @[FIFOs.scala 108:19]
        node _T_6 = eq(_T_5, headReg) @[FIFOs.scala 108:26]
        when _T_6 : @[FIFOs.scala 108:39]
          emptyReg <= UInt<1>("h1") @[FIFOs.scala 109:16]
    io.empty <= emptyReg @[FIFOs.scala 113:12]
    infer mport io_dataOut_MPORT = memRegs[tailReg], clock @[FIFOs.scala 114:24]
    io.dataOut <= io_dataOut_MPORT @[FIFOs.scala 114:14]
    node _io_full_T = eq(tailReg, headReg) @[FIFOs.scala 115:23]
    node _io_full_T_1 = eq(emptyReg, UInt<1>("h0")) @[FIFOs.scala 115:38]
    node _io_full_T_2 = and(_io_full_T, _io_full_T_1) @[FIFOs.scala 115:36]
    io.full <= _io_full_T_2 @[FIFOs.scala 115:11]

  module mycompareFIFOs :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip dataIn : UInt<4>, flip push : UInt<1>, flip pop : UInt<1>}

    inst resetCounter of ResetCounter @[Formal.scala 10:36]
    resetCounter.notChaos is invalid
    resetCounter.timeSinceReset is invalid
    resetCounter.reset is invalid
    resetCounter.clk is invalid
    resetCounter.clk <= clock @[Formal.scala 11:23]
    resetCounter.reset <= reset @[Formal.scala 12:25]
    inst srFIFO of srFIFO @[FIFO_T.scala 71:24]
    srFIFO.clock <= clock
    srFIFO.reset <= reset
    inst rbFIFO of rbFIFO @[FIFO_T.scala 72:24]
    rbFIFO.clock <= clock
    rbFIFO.reset <= reset
    srFIFO.io.dataIn <= io.dataIn @[FIFO_T.scala 74:19]
    srFIFO.io.push <= io.push @[FIFO_T.scala 75:17]
    srFIFO.io.pop <= io.pop @[FIFO_T.scala 76:16]
    rbFIFO.io.dataIn <= io.dataIn @[FIFO_T.scala 78:19]
    rbFIFO.io.push <= io.push @[FIFO_T.scala 79:17]
    rbFIFO.io.pop <= io.pop @[FIFO_T.scala 80:16]
    node _T = eq(srFIFO.io.empty, rbFIFO.io.empty) @[FIFO_T.scala 82:25]
    when resetCounter.notChaos : @[FIFO_T.scala 82:11]
      node _T_1 = bits(reset, 0, 0) @[FIFO_T.scala 82:11]
      node _T_2 = eq(_T_1, UInt<1>("h0")) @[FIFO_T.scala 82:11]
      when _T_2 : @[FIFO_T.scala 82:11]
        assert(clock, _T, UInt<1>("h1"), "") : assert @[FIFO_T.scala 82:11]
        node _T_3 = eq(_T, UInt<1>("h0")) @[FIFO_T.scala 82:11]
        when _T_3 : @[FIFO_T.scala 82:11]
          printf(clock, UInt<1>("h1"), "Assertion failed: \n    at Formal.scala:20 cassert(cond, msg)\n") : printf @[FIFO_T.scala 82:11]
    node _T_4 = eq(srFIFO.io.full, srFIFO.io.full) @[FIFO_T.scala 83:24]
    when resetCounter.notChaos : @[FIFO_T.scala 83:11]
      node _T_5 = bits(reset, 0, 0) @[FIFO_T.scala 83:11]
      node _T_6 = eq(_T_5, UInt<1>("h0")) @[FIFO_T.scala 83:11]
      when _T_6 : @[FIFO_T.scala 83:11]
        assert(clock, _T_4, UInt<1>("h1"), "") : assert_1 @[FIFO_T.scala 83:11]
        node _T_7 = eq(_T_4, UInt<1>("h0")) @[FIFO_T.scala 83:11]
        when _T_7 : @[FIFO_T.scala 83:11]
          printf(clock, UInt<1>("h1"), "Assertion failed: \n    at Formal.scala:20 cassert(cond, msg)\n") : printf_1 @[FIFO_T.scala 83:11]
    node _T_8 = eq(srFIFO.io.empty, UInt<1>("h0")) @[FIFO_T.scala 84:10]
    when _T_8 : @[FIFO_T.scala 84:25]
      node _T_9 = eq(srFIFO.io.dataOut, rbFIFO.io.dataOut) @[FIFO_T.scala 85:31]
      when resetCounter.notChaos : @[FIFO_T.scala 85:15]
        node _T_10 = bits(reset, 0, 0) @[FIFO_T.scala 85:15]
        node _T_11 = eq(_T_10, UInt<1>("h0")) @[FIFO_T.scala 85:15]
        when _T_11 : @[FIFO_T.scala 85:15]
          assert(clock, _T_9, UInt<1>("h1"), "") : assert_2 @[FIFO_T.scala 85:15]
          node _T_12 = eq(_T_9, UInt<1>("h0")) @[FIFO_T.scala 85:15]
          when _T_12 : @[FIFO_T.scala 85:15]
            printf(clock, UInt<1>("h1"), "Assertion failed: \n    at Formal.scala:20 cassert(cond, msg)\n") : printf_2 @[FIFO_T.scala 85:15]

